In AXI, a burst is an efficient method for transferring multiple data items within a single transaction, initiated by a single address.
Understanding AXI Bursts
Based on the provided reference, an AXI 'burst' is a transaction in which multiple data items are transferred based upon a single address. This means instead of sending a new address for every single piece of data to be read or written, the master initiates a transaction with one address and specifies the number of data items to be transferred consecutively.
Each individual data item transferred during a burst is referred to as a 'beat'. So, a burst is composed of one or more beats.
Key Concepts
- Efficiency: Bursts significantly improve bus efficiency by reducing the overhead associated with sending address and control signals for each data transfer.
- Single Address: The entire sequence of data transfers in a burst starts from a single initial address.
- Multiple Data Items (Beats): A burst allows the transfer of multiple data items (beats) back-to-back.
- Burst Length: The number of beats in a burst is specified by the master. AXI supports burst lengths typically up to 16 beats (in AXI3) or variable lengths (in AXI4).
Why Use Bursts?
Using bursts offers several advantages in system-on-chip (SoC) designs that utilize the AXI protocol:
- Increased Throughput: By minimizing the time spent on address and control phases, more bus cycles can be dedicated to data transfer, leading to higher data throughput.
- Reduced Power Consumption: Less signaling activity per data item can contribute to lower power consumption compared to single transfers.
- Simplified Master/Slave Logic: Masters can initiate large data transfers with a single request, and slaves can optimize their data access based on burst information.
Types of AXI Bursts
AXI defines different burst types to support various memory access patterns:
- FIXED: The address remains constant for every beat in the burst. Useful for accessing FIFOs or register banks where the address doesn't increment.
- INCR (Incrementing): The address for each subsequent beat increments from the initial address by the size of the data item. This is the most common type for sequential memory access.
- WRAP: Similar to INCR, but the address wraps around to a lower address within a defined boundary if it exceeds the boundary. This is useful for accessing cache lines or circular buffers.
These burst types are signaled using the AxBURST signals on the AXI bus.
By utilizing bursts, AXI facilitates high-performance data movement between components in complex digital systems.
