Skew latency, often referred to as clock skew, describes a critical timing phenomenon in digital circuits. Fundamentally, the latency difference between two related flops in a design is called as local skew.
In synchronous digital design, all flip-flops (flops) are ideally triggered by the same clock signal arriving simultaneously. However, due to variations in wiring paths, buffers, and physical layout, the clock signal arrives at different flops at slightly different times. This difference in clock arrival times is known as clock skew, and it manifests as a latency difference.
Understanding Local Skew
The provided reference defines local skew specifically as the latency difference between two flops that are related, typically a launch flop and a capture flop connected by a data path. This local skew is crucial for timing analysis, particularly setup and hold time checks.
The calculation involves comparing the clock arrival time (clock latency) at the capture flop with the clock arrival time at the launch flop.
Calculating Local Skew: An Example
Let's illustrate with the example provided in the reference:
Suppose we have two related flops:
- FF1: The Launch Flop (where data originates in the current clock cycle).
- FF2: The Capture Flop (where data is intended to be captured in the next clock cycle).
The clock signal travels through clock distribution networks to reach these flops. The time it takes for the clock edge to arrive at a flop is its clock latency.
Based on the reference example:
| Flop | Clock Latency Calculation | Clock Latency |
|---|---|---|
| FF1 | 10 + 10 | 20 ps |
| FF2 | 10 + 10 + 10 + 10 | 40 ps |
- Launch Clock Latency: The time for the clock edge to reach FF1 is 20 ps.
- Capture Clock Latency: The time for the clock edge to reach FF2 is 40 ps.
The Local Skew is the difference between the Capture Clock Latency and the Launch Clock Latency.
Local Skew = Capture Clock Latency - Launch Clock Latency
Local Skew = 40 ps - 20 ps = +20 ps
A positive skew, as in this example (+20 ps), means the clock arrives later at the capture flop (FF2) than at the launch flop (FF1). A negative skew would mean the clock arrives earlier at the capture flop.
Impact of Skew Latency
Skew latency (clock skew) can significantly impact the reliable operation of a digital circuit:
- Setup Time Violations: If the clock arrives too late at the capture flop relative to the launch flop (positive skew), the data might not be stable at the capture flop's input before the clock edge arrives, leading to a setup time violation.
- Hold Time Violations: If the clock arrives too early at the capture flop relative to the launch flop (negative skew), the data from the previous cycle might change too soon after the clock edge arrives, leading to a hold time violation.
- Cycle Time Reduction: Skew reduces the effective time available for data to propagate between flops, potentially forcing a reduction in the circuit's clock frequency.
Managing and minimizing clock skew is a critical task in digital design and physical layout to ensure correct timing and maximum performance.
