Assertion-Based IP (AIP) refers to pre-verified intellectual property (IP) cores designed specifically to be used with formal verification tools in a formal verification environment. The key purpose of AIP is to enhance the efficiency and reliability of formal verification processes.
In essence, AIP provides a set of synthesizable assertions embedded within the IP core's RTL (Register Transfer Level) code. These assertions act as formal properties that can be checked by formal verification tools to prove the correctness of the IP core's behavior.
Here's a breakdown of key aspects:
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Formal Verification Focus: The primary intention of AIP is to facilitate formal verification, ensuring a design meets its specifications. This requires the AIP to be written in a way that's easily analyzed by formal tools.
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Synthesizability: AIP needs to be synthesizable. This means the assertions within the IP can be translated into actual hardware logic. While the assertions are primarily used for verification, they should not introduce non-synthesizable constructs that would prevent the IP from being implemented in hardware.
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Coding Guidelines: Specific coding guidelines are followed when creating AIP to ensure it's "formal tool friendly." These guidelines aim to make the verification process more efficient and to reduce the complexity of the proofs.
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Assertions as Properties: The embedded assertions represent key functional properties of the IP. These properties are then checked by formal verification tools to rigorously prove the IP's correct operation across all possible input scenarios, within the defined constraints and assumptions.
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Early Bug Detection: By using AIP and formal verification, potential design errors can be identified much earlier in the development cycle, reducing the risk of costly re-spins and delays.
In summary, Assertion-Based IP provides pre-verified building blocks for hardware design, enabling more robust and efficient formal verification, ultimately leading to higher quality designs.
