In the context of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and semiconductor manufacturing, pitch refers to the center-to-center distance between identical, repeating features on the silicon wafer. It's a critical dimension that dictates how closely transistors and other components can be packed together on a chip.
While "pitch" can refer to various recurring dimensions (like contact pitch or metal layer pitch), it most commonly refers to the gate pitch when discussing transistor density and scaling. The gate pitch is the distance from the center of one transistor gate to the center of an adjacent transistor gate.
Understanding MOSFET Pitch and Density
The ability to shrink the pitch is fundamental to increasing the number of transistors on a chip, following Moore's Law. A smaller pitch means more transistors can fit into the same area, leading to improved performance, lower power consumption, and reduced cost per transistor.
Key Aspect of Pitch Scaling:
- Density: Reducing the pitch allows for higher transistor density.
- Performance: Smaller dimensions often lead to faster switching speeds.
- Power: Reduced leakage currents and capacitance can lower power consumption.
Pitch Scaling and Technology Nodes
Semiconductor manufacturing progresses through different "technology nodes" (often denoted by nanometer values like 90nm, 45nm, 22nm, 7nm, etc.). These nodes historically related to the gate length, but now represent a generation of technology with a specific set of minimum feature sizes and pitches.
According to the provided reference:
MOSFET pitch is scaled by a factor of 0.7 per technology node to accommodate for doubling of transistor count, but a slow-down is seen in recent years.
This statement highlights a historical trend:
- Scaling Factor: Traditionally, key dimensions like pitch were scaled by approximately 0.7 (which is roughly $1/\sqrt{2}$) from one technology node to the next.
- Impact on Area: Scaling pitch by 0.7 in both X and Y directions reduces the area occupied by a feature (and thus the transistor layout) by roughly $0.7 \times 0.7 = 0.49$, or about half.
- Transistor Count: This halving of area per transistor allows the transistor count to double per technology node in the same chip area, which is the core driver of Moore's Law.
- Recent Trends: The reference notes a "slow-down" in this aggressive scaling in recent years, indicating that achieving the 0.7 scaling factor has become increasingly challenging due to physical limitations.
Examples of Pitch in MOSFET Layout
While gate pitch is a primary example, other pitches are also crucial:
- Gate Pitch: Center-to-center distance between adjacent transistor gates. Directly impacts transistor density along one axis.
- Fin Pitch (for FinFETs): In 3D transistor structures like FinFETs, this is the distance between the centers of adjacent silicon fins. Impacts density and performance.
- Contact Pitch: Distance between the centers of adjacent electrical contacts connecting the transistor to the metal layers above. Critical for routing and interconnections.
- Metal Pitch: Distance between the centers of adjacent lines on a specific metal interconnection layer. Determines wiring density.
Understanding and controlling these pitches is fundamental to designing and manufacturing modern microprocessors and other integrated circuits.
